关于vhdl的问题
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ADDER4B IS
PORT(C4: IN STD_LOGIC;
A4: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
B4: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S4: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
CO4:OUT STD_LOGIC);
END ENTITY ADDER4B;
ARCHITECTURE ART OF ADDER4B IS
SIGNAL S5:STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL A5,B5:STD_LOGIC_VECTOR(4 DOWNTO 0);
BEGIN
A5<=’0’&A4;
B5<=’0’&B4;
S5<=A5+B5+C4;
S4<=S5(3 DOWNTO 0);
CO4<=S5(4);
END ARCHITECTURE ART;
这是vhdl程序，但我没学过，我想知道这程序的意思，谁可以帮我注释一下，要详细的，我把40分都给他，谢谢了。
[解决办法]
长见识了,没想到集成电路也有开发语言
这个世界真奇妙
